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FPGA教程之频率简介

时间：2014-05-02 来源：123485.com 作者：9stone

FPGA教程之频率简介

每个CPU都有一个工作频率，FPGA也不例外（当然，只有你的设计应该是时序逻辑），那该频率是根据什么形成的呢？

首先，我们来分析16-bit计数器，通过该用例，掌握QuartusII的时序分析器及了解一个时序逻辑频率的概念。源代码如下（QuautusII7.2SP3，EP2C35F484C8）：

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;

entity counter is

port(

rst: in std_logic;

clk: in std_logic;

carry: out std_logic

);

end counter;

architecture synlogic of counter is

signal r_cnt: std_logic_vector(15 downto 0);

begin

process(rst, clk)

begin

if rst = '1' then

r_cnt <= (others => '0');

elsif rising_edge(clk) then

r_cnt <= r_cnt + '1';

end if;

end process;

carry <= '1' when r_cnt = X"FFFF" else '0';

end synlogic;

建立工程，将所有的输入输出管脚分配为Virtual Pin，其中时钟管脚Virtual Pin Clock，表示该工程没有实际输入输出管脚，方法如下：

单击菜单Assignments/Assignment Editor，打开窗口Assignment Editor；

然后，右键“To”列下的“《new》”，选择“Node Finder…”；

其次，单击“List”，选择“Carry”，“clk”，“rst”到右边的“Selected Nodes”，单击OK返回；

而后，在Assignment Name下面分别选择“Virtual Pin”，“Virtual Pin Clock”，“Virtual Pin”，并且在Value列下都选择“On”，保存；

最后，对其进行全编译；

观察“Compilation Report/Timing Analyzer/Clock Setup：‘clk’”， Fmax从小到大排列，取其中最小的Fmax值，得Fmax = 293.86MHz，则表示该十六位计数器最快可以运行在293.86MHz。那该频率主要是受什么因素影响？首先，我们先看Fmax的定义，在QuartusII的帮助中有如下说明：

The maximum clock frequency that can be achieved without violating internal setup (tSU) and hold (tH) time requirements. Unrestricted fMAX is the maximum frequency at which a design can run. Restricted fMAX is the maximum frequency a design can run considering device limits, such as maximum toggle rates. The Classic Timing Analyzer analyzes and reports fMAX following timing analysis.

You can specify the fMAX required by default for a design in the Classic Timing Analysis Settings page of the Settings dialog box. You can also specify the required fMAX of individual clock signals in a design by creating clock settings and assigning them to signals in the design.

The Classic Timing Analyzer calculates fMAX with the following equation:

fMAX = 1/(<register to register delay> - <clock skew delay> + <micro setup delay> + <micro clock to output delay>)

Clock skew delay is calculated with the following equation:

<clock to destination register delay> - <clock to source register delay>，即Tcd2 – Tcd1。

从表达式可以知道，Fmax主要受以下四个因素影响：register to register delay/寄存器到寄存器延时Tnet，clock skew delay/寄存器间时钟偏斜，micro setup delay/LC中的D触发器建立时间Tsetup，micro clock to output delay/ LC中的D触发器时钟输出延时Tcko。如下图：

下面，我们具体计算一下293.86MHz的得出：