Drive Level(DLD)(激励功率依赖性)
The amplitude of mechanical vibration of the quartz resonator increases proportionally to the amplitude of the applied current．The power dissipated in the resonance resistance is given by Pc=12qRl．High drive levels lead to the destruction of the resonator or the vaporisation of the evaporated electrodes，The upper limit for drive level is approximately 10 mV
As the reactive power oscillating between L1 and C1 is represented by Qc=Q X Pc，for Pc=1 MW and with a Q of 100.000，Qc is equal to 100Watts，The oscillation amplitude can be exceeted with relatively low level of drive Pc，thus resulting in the crystal frequency moving upwards．
This frequency dependence on drive level is more pronounced with increasing overtone order．Figure 9 shows typical effects but exact prediction of the effect is not possible as it is influenced by all the elements of crystal design and operation．
Mechanical blank parameters．mounting arrangements and so on．Is it can be seen that the drive level must be specified carefully．if there iS to be good correlation between the frequency of the crystal at the end of its production and in the end use equipment．
Today with semiconductor oscillator circuits a drive level of approximately 0.1 MW appears normal．where this parameter is most specified．our
production will use 0.1 Mw．
A well performing crystal should start to oscillate easily and its frequency should be virtrally independent of the variation of drive level from a starting level of about 1 nW．In todays semiconductor circuits with very low power consumption the crystal has to work well also at very low drive levels．
In fig.10 we show the effect of crystals with and without the problem of frequency dependence on drive level．
Crystal that have badly adhering electrodes or on which the Surface of the resonator is not fine enough exhibit the curved effect．At low drive level they have higher resistance．
This effect is called the drive level dependence (DLD)．Usually production tests of DLD are performed between 1 and 10 microwatts and then at 1 Mw and again at a low load．The relative change in resistance is then used as the test criterion．Needless to say．making more measurements intermediate level increases production costs considerably．
Using suitable test oscillators permits fast of the DLD limit value．but only in the form of a Go/No-go test．IEC Draft 248 covers measurement of the drive level dependence of the resonance impedance in accordance with (DIN) IEC444-6．
Oscillation build—up problems can very largely be eliminated by optimizing the oscillator circuit by providing a sufficient feedback reserve and a "hard" switch-on pulse．
石英振荡器的机械振动的振幅会随着电流的振幅成正比例地上升．功率与响应阻抗的关系为Pc=l2qR1，高激励功率会导致共振的破坏或蒸镀电极的蒸发，最高允许的功率不应超过lOmV．
由于L1和C1电抗性的功率振荡，存在Qc=QxPc．若Pc=1mV Q=100.000，Qc则相当于IOOW．由于低的Pc功率会导致振荡幅度的超过，最终导致晶体的频率上移．
随着晶体泛音次数的增加，对于激励功率的依赖性更加显著．上图显示了典型的结果，但是精确的预期结果还是要受到包括晶体设计和加工，机械性芯片参数，电极大小，点胶情况等的影响．
可以看出，激励功率必须被谨慎地确定，以使晶体在生产中和使用中保持良好的关系．
当今，一个半导体振荡回路的激励功率一股为0。1mV故在生产晶体时也一股按0.1mV进行．
一个质量良好的晶体可以容易地起振，其频率在自lnW逐步增加时均能保持稳定．现在，晶体两端的功率很低的半导体回路也可以在很低的功率的情况下工作良好．
上图显示了一个对激励功率有或无依赖性的晶体的工作曲线的比较．
晶体存在蒸镀电极不良，芯片表面洁净度不足，都会存在如图所示的在低功率时出现高阻抗的情况，这一影响称为激励功率依赖。(DLD)．通常生产中测试DLD是用1～lOmV测试后再用lmV测试，发生的阻抗变化可作为测试的标准．很显然，在增加测试内容会相当大的提高晶体生产的成本．
利用适当的测试仪器可以很快地进行DLD极限值的测定，但是只能进行合格/不合格的测试．IEC草案248覆盖了根据(DIV)IEC444-6制定的激励功率的依赖性的测量方法．
提供具有充分的回馈和良好脉冲的最优化的振荡回路，可以极大的消除振荡的内部问题．
Notes for Crystal Unit Applications(石英晶体谐振器使用的注意点)
(1) Compared with the lineups of HC-49/U，small crystal units (HC-49U/S，HC-49USM，UM-1，SMD)are designed to have lower limitable
level of drive，of 100uW and below．Prior to use，therefore，the crystal current should be examined in an actually mounting circuit．(See Fig.5.)
(2) The negative resistance of a circuit must be checked．Confirmation of negative resistance is possible according to Fig.6.A goal of negative
resistance is about 5 times the resonance resistance．
(3)The Rd in the circuit diagram is indispensable when used in a C-MOS oscillation circuit．(See fig7．)lf this Rd is attached，the level of drive is kept within the specified value and stable oscillation frequency can be obtained．
(4)Cg and Cd should be used within the range of 10-30pf，if Cg and Cd are used below 10pF or above 30pF．oscillation may be easily affected by circuit performance．level of drive may increase．or negative resistance may decrease，thus failing in maintaining stable oscillation．
(5) The layout for crystal oscillation circuits should be arranged as short as possible．
(6) The stray capacitance between circuits and ground patterns should be reduced．
(7)Crossing of crystal oscillation circuit patterns over other circuit patterns should be avoided．
(8)If the circuits used，IC types，and IC manufacturers are different，frequency．level of drive．and negative resistance should be confirmed．
(9) Overtone oscillation circuits need additional consultation．
(1)与HC-49/U相比，小的石英晶体谐振器(如HC-49U/S，HC-49USM，UM-1，49T)都是低激励功率(100um或以下)．在使用之前，须在一个实际的安装电路中检验晶体电流(见图5)．
(2)须检查电路的负阻抗，负阻抗的认可见图8．负阻抗应是谐振阻抗的5倍左右．
(3)当使用C-MOS振荡器时(见图7)线路图中的Rd是必要的．如果Rd达到要求，激励功率会保持在规定值内，那么谐振频率也就稳定了．
(4)在10—30PF内，可以用Cg和Cd，如果Cg和Cd<10PF或>30PF，振荡会被电路现象轻易的影响，激励功率会升高，或负阻抗会减小，最终导致振荡的不稳定．
(5)晶体振荡电路的设计应尽量简短．
(6)电路和线路板问的杂散电容应尽量被减少．
(7)尽量避免晶体振荡电路穿过其它电路．
(8)如果电路用IC方式，而且IC制造各不相同，那么频率，激励功率，负阻抗须被确认．
(9)泛音振荡电路还需要附加的参考．
Notes for Ordering(定货注意点)
For special use conditions more detailed specifications should be offered，if more detailed specifications should be offered，if more practical applications，etc.. are specified．the most suitable products can be introduced．When load capacitances，etc.，are unclear for crystal units，the result will be more advantaaeous if the circuit being adopted or the actual device．
石英晶体振荡器的一个典型应用(石英钟表)
1、石英钟走时准、耗电省、经久耐用为其最大优点。不论是老式石英钟或是新式多功能石英钟都是以石英晶体振荡器为核心电路，其频率精度决定了电子钟表的走时精度。石英晶体振荡器原理的示意如图3所示，其中V1和V2构成CMOS反相器石英晶体Q与振荡电容C1及微调电容C2构成振荡系统，这里石英晶体相当于电感。振荡系统的元件参数确定了振频率。一股Q、C1及C2均为外接元件。另外R1为反馈电阻，R2为振荡的稳定电阻，它们都集成在电路内部。故无法通过改变C1或C2的数值来调整走时精度。但此时我们仍可用加接一只电容C有方法，来改变振荡系统参数，以调整走时精度。根据电子钟表走时的快慢，调整电容有两种接法：若走时偏快，则可在石英晶体两端并接电容C，如图4所示。此时系统总电容加大，振荡频率变低，走时减慢。若走时偏慢，则可在晶体支路中串接电容C。如图5所示。此时系统的总电容减小，振荡频率变高，走时增快。只要经过耐心的反复试验，就可以调整走时精度。因此，晶振可用于时钟信号发生器。
电路组成下图1示出的60Hz脉冲信号发生电路，由石英晶体多谐振荡器和分频器两部分电路组成，其中ICl为“非”门电路CD4069，IC2为分频集成电路CD4040，JT为32768Hz石英晶体。
石英晶体、“非”门1和“非”门2组成石英晶体多谐振荡器，晶体JT和电容C1在电路中形成正反馈。晶体在它的固有串联谐振频率点f0的等效阻抗最小，所以电路的振荡频率就取决于晶体的固有串联谐振频率，与外接电阻R1、电容C1的参数无关。由于石英晶体的频率稳定度可达10—10～10—11，所以可获得频率非常稳定的振荡信号。IC2、“非”门3、“非”门4和D1、D2组成分频电路，它对石英晶体振荡器所产生的32768Hz的脉冲信号进行分频，在输出端010或09可获取60Hz的脉冲信号。
分频比及频率误差CD4040是一片12级脉动进位二进制计数分频电路，它在时钟的下降沿进行计数，其复位端输入高电平时，可取得与时钟输入无关的直接复位。由于石英晶体的固有谐振频率f0=32768Hz，从Q9端输出的信号是f0的29分频，其数值是64Hz，所以不采取一定的措施是不能获得60Hz的信号的。所采取的措施是，把CD4040的010输出端通过R2、“非”门3和“非”门4连接到它的复位端，同时通过D1、D2分别连接到它的Q2和Q6输出端，即D1、D2、“非”门3和“非”门4组成复位控制电路，让Q10、Q6、Q2的输出共同控制CD4040的复位。
Q10端输出的信号是振荡频率的210分频，该信号的一个周期为振荡脉冲信号的1024个周期时间，低电平和高电平时间各为振荡脉冲的512个周期时间。同理，Q6端输出信号一个周期的高、低电平各为振荡脉冲的32个周期时间，Q2端输出信号一个周期的高、低电平时间各为振荡脉冲的2个周期时间。它们在Q10上升沿处的波形如图2所示。由于CD4040是下降沿触发，所以在Q10的上升沿处对应着Q6的下降沿。从图1可见，CD4040在Q10、Q6和Q2均为高电平(即Q10‘Q6‘Q1=1)时复位。从图2可以看出，电路复位出现在Q10高电平，Q6也高电平之后，Q2输出第一个高电平的时刻。电路复位时Q10、Q6、Q2均回到低电平，Q10以及Q9输出脉冲结束一个周期，开始新的周期。
从上面分析可以得出09、010输出脉冲信号的周期为512+32+2=546振荡脉冲周期时间，它们的频率就是振荡脉冲信号的546次分频，因此其频率为：
f=32768/546≈60.01465201Hz，其误差为6=(60.01465201-60)/60≈2.442×10-4。
减小误差的电路为了减小输出脉冲信号的频率误差，可以适当修正振荡脉冲信号的频率，具体做法是在电路上把图1的石英器件多谐振荡电路改为图3所示的可微调频率的石英晶体多谐振荡电路。石英晶体JT仍作为反馈元件，“非”门电路工作在线性放大状态，R1为其提供偏置。当振荡频率接近晶体的固有串联谐振频率时，电路满足振荡条件。该电路仍具有十分稳定的振荡频率。
图3中C1、C2和石英晶体JT组成兀形反馈网络，调整C1或C2的值，可以微调电路的振荡频率。
该电路的输出端接到图1中CD4040的CLK端，输出的脉冲信号作为CD4040的计数脉冲。要使图1中CD4040的09和010输出60Hz的脉冲信号，计数脉冲的频率应为：f0=60×546=32760Hz。
这一振荡频率在图3所示的电路中可通过调整C1或C2的数值来实现。
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