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VCS-verilog compiled simulator是synopsys公司的产品.其仿真速度相当快,而且支持多种调用方式;使用的步骤和modelsim类似,都要先做编译,再调用仿真.
Vcs包括两种调试界面:Text-based:Command Line Interface(CLI) 和 GUI-based(VirSim);仿真主要的两个步骤是编译,运行:
>vcs design.v
//编译verilog的源文件并且生成一个可执行文件simv
>simv
//运行simv
一般情况下都存在vcs 做编译的时候的compile_time_options和运行时候的run_time_options,这些我们在下面再具体介绍. 一.VCS的三种调试模式
使用vcs存在三种调试模式:CLI调试模式,VirSim交互调试模式和VirSim后处理调试模式.下面举例说明:
1. CLI调试模式
CLI调试模式存在两种调用方法,一种是编译后马上执行,一种是把编译执行分开处理
>vcs source.v +cli+3 –R –s
或者
>vcs source.v +cli+3
>simv source.v –s
其中 +cli+[1 2 3 4]是指调试时候交互调试的能力.
+cli+[<module_name>=]1|2|3|4
Enable CLI debugging.
1 enables you to see the values of nets and registers and deposit values to registers.
2 also enables breakpoints on value changes of nets and registers.
3 also enables you to force a value on nets.
4 also enables you to force a value on a register.
You can specify a module to enable CLI debugging only for instances of the module.
-line 能够支持单步调试 但是这些都是会增加运行时间的.
这里不详细介绍CLI 命令具体可以参考usrerguide.注意我们也可以把CLI的命令写成一个script的文件在vcs编译时调用.
>vcs source.v –R –s –include script_file
或者在cli下调用cli>source script_file
2. VirSim交互调试模式
启动VirSim交互调试模式和调用CLI一样也是有两中方法.
>vcs source.v –RI –line +vcsd +cfgfile+filename
或者
>vcs source.v –I –line +vcsd
>vcs source.v -RIG +cfgfile+filename
其中-RI 作用有两个:编译生成可以在VirSim中可执行的文件并且编译后马上启动Virsim;
要编译成可以在VirSim中可执行的文件必须在编译阶段加-I,在要生成vcd或vpd时这个参数一定要添加;-RIG通过一个已编译完成的默认的simv文件启动Virsim,在启动之前一定要通过vcs –RI或者-I对源文件做过编译.
使用vcs编译源文件之后会发现目录下多了simv和/csrc等文件,其中simv是默认的可执行文件,可以在vcs做编译的时候 –o filename改变输出的名字,/csrc是存的增量编译的结果,/simv.daidir如果设置中使用到了PLI就会创建.
具体如何使用VirSim做交互调试这里也不具体介绍,可以参考VirSim的userguide和vcs安装下面的doc的tutorial.
3. VirSim的后处理调试模式
注意什么时候用后处理调试模式,什么时候使用交换模式那?在初步仿真的过程使用交
互模式,若是调试一个成熟的设计或者很多人一起做调试这样子可以使用post-processing mode.其主要的方法是通过仿真运行dump数据在vcd或者vpd文件中,运行结束后通过vcd或者vpd观察运行过程的情况,交互调试能力相对较差,但是通过记录的数据可以观察出其中异常的地方;也就是包括两个步骤Write VCD+ file,View result.
>vcs source.v –line –R -PP +vcsd
其中-R自动运行并且生成vcd+文件
-PP编译的时候是faster VirSim post_processing
>vcs –RPP source.v +vpdfile+vcdplus.vpd
注意:VirSim只能处理VCD+ file.VCD文件可以被转换成VCD+格式的文件.
VCD+和VCD有什么不一样那?更快,更小.
VCD+系统任务可以在testbench中使用也可以在仿真的时候添加.(注意使用到这些系统函数时,在vcs编译的时候一定要添加-I或者-RI.)
$vcdpluson(level_number,module_instance,….|net_or reg,….)
level_numbers
指定记录的层次
0- 记录整个指定module_instance的所有信号
1- 记录指定module_instance顶层信号
n- 记录从顶层开始到下面的n层例化模块的信号
module_instance 指定例化名
net_ or reg 指定特定的wire或者reg作为记录的对象,默认是所有信号.
$vcdplusoff(module_instance,….|net_ or reg,…)
其他系统函数可以参见VCS quick reference. 二. 其他情况
注意区别的两个方面:
1. –R –I 不同于-RI
-R –I是编译成VirSim的可执行文件而且马上运行仿真, -RI是编译成VirSim的可执行文件并且调用VirSim.
2. –R –PP 不同于-RPP
-R –PP是编译成VirSim的可执行文件并且在运行的时候加快输出VCD+文件
-RPP是在存在VCD+的条件下调用VirSim进行post processing的调试.
门级仿真需要反标SDF文件,可以在testbench中添加$sdf_annotate系统函数.并且在编译的时候注意要使用standcell的仿真库. Compile-Time Options
********************
-f <filename>
Specifies a file that contains a list of pathnames to source files
and compile-time options.
-F <filename>
Same as the -f option but allows you to specify a path to the file
and the source files listed in the file do not have to be absolute
pathnames.
-h
Displays a succinct description of the most commonly used compile-time
and runtime options.
-l <filename>
(lower case L) Specifies a log file where VCS records compilation
messages and runtime messages if you include the -R, -RI, or
-RIG options.
-line
Enables stepping through the code and source line breakpoints in VirSim.
-M
Enables incremental compilation, but do not overwrite the makefile.
-Mupdate
Enable incremental compilation and overwrite the make file.
-notice
Enables verbose diagnostic messages.
-o <name>
Specifies the name of the executable file that is the product of
compilation. The default name is simv (simv.exe on Windows).
-ova_cov
Enables functional coverage.
-P <pli.tab>
Specifies a PLI table file.
-R
Run the executable file immediately after VCS links together the
executable file. You can add any runtime option to the vcs command
line.
-s
Stop simulation just as it begins. Use this option with the -R and
+cli options.
-timescale=<time_unit>/<time_precision>
If only some source files contain the `timescale compiler directive
and the ones that don't appear first on the vcs command line, use
this option to specify the time scale for these source files.
-V
Enables the verbose mode.
-v <filename>
Specifies a Verilog library file to search for module definitions.
-vera
Specifies the standard VERA PLI table file and object library.
-y <directory_pathname>
Specifies a Verilog library directory to search for module
definitions.
+2state
Enables 2 state simulation.
+cli+[<module_name>=]1|2|3|4
Enable CLI debugging.
1 enables you to see the values of nets and registers and deposit
values to registers.
2 also enables breakpoints on value changes of nets and registers.
3 also enables you to force a value on nets.
4 also enables you to force a value on a register.
You can specify a module to enable CLI debugging only for instances
of the module.
+define+<macro_name>=<value>
Defines a text macro. Test for this definition in your Verilog
source code using the `ifdef compiler directive.
+incdir+<directory>
Specifies the directories that contain the files you specified with
the `include compiler directive. You can specify more that one
directory, separating each path name with the + character.
+libext+<extension>
Specifies that VCS only search the source files in a Verilog library
directory with the specified extension. You can specify more than one
extension, separating each extension with the + character.
For example, +libext++.v specifies searches library files with no
extension and library files with the .v extension.
Enter this option when you enter the -y option.
+maxdelays
Use maximum value when min:typ:max values are encountered in delay
specifications SDF files.
+mindelays
Use minimum value when min:typ:max values are encountered in delay
specifications and SDF files.
+notimingcheck
Suppresses timing checks in specify blocks.
+plusarg_ignore
Also enter this option in the file that you specify with the -f option
so that VCS does not pass to the simv executable or to VirSim the
options that follow in the file. Use this option with the
+plusarg_save option to specify that other options should
not be passed.
+race
Specifies that VCS generate a report, during simulation, of all the
race conditions in the design and write this report in the race.out
file.
+race=all
Analyzes the source code during compilation to look for coding
styles that cause race conditions.
+rad or +rad+2
Performs aggressive optimizations on your design.
+rad+1 or +radlite or +radlight
Performs less aggressive optimizations on your design.
+v2k
Enables the use of new Verilog constricts in the 1364-2001 standard. Runtime Options
***************
-i <filename>
Specifies a file containing CLI commands that VCS executes when
simulation starts.
-l <filename>
Specifies writing all messages from simulation to the specified
file as well as displaying these messages in the standard output.
This option begins with the letter "l" (lowercase "L") for log file.
-ova_cov
Enables functional coverage reporting.
-s
Stops simulation just as it beings, and enters interactive mode.
Use with the +cli+<number> option.
-V
Verbose mode. Print VCS version and extended summary information.
Prints VCS compile and run-time version numbers, and copyright
information, at start of simulation.
-vcd <filename>
Sets the output VCD file name to the specified file.
The default filename is verilog.dump.
A $dumpfile system task in the Verilog source code will override
this option.
+maxdelays
Species using the compiled SDF file for maximum delays generated
by the +allmtm compile-time option.
Also specifies using maximum delays for SWIFT VMC or SmartModels
or Synopsys hardware models if you also enter the
+override_model_delays runtime option.
+mindelays
Specifies using the compiled SDF file for minimum delays generated
by the +allmtm compile-time option.
Also specifies using minimum delays for SWIFT VMC or SmartModels
or Synopsys hardware models if you also enter the
+override_model_delays runtime option.
+notimingcheck
Suppress timing checks.
+override_model_delays
Enables you to use the +mindelays, +typdelays, or +maxdelays runtime
options to specify timing for SWIFT SmartModels or Synopsys hardware
models.
+sdfverbose
Enables the display of more than ten warning and ten error messages
about SDF back annotation.
+vcs+dumpoff+<t>+<ht>
Turn off value change dumping ($dumpvars system task) at time <t>.
<ht> is the high 32 bits of a time value greater than 32 bits.
+vcs+dumpon+<t>+<ht>
Suppress $dumpvars system task until time <t>.
<ht> is the high 32 bits of a time value greater than 32 bits.
+vcs+dumpvarsoff
Suppress $dumpvars system tasks.
+vcs+finish+<t>+<ht>
Finish simulation at time <t>.
<ht> is the high 32 bits of a time value greater than 32 bits. Options for Using VirSim Interactively or in Post-Processing
************************************************************
+cfgfile+<filename>
Specifies using a configuration file that you recorded in a
previous session with VirSim.
+vslogfile[+<filename>]
Enables logging of VirSim commands in a VirSim log file. If you do not
specify a filename, the log is automatically saved to the working
directory as VirSim.log.
Options For Using VirSim
************************
the following are options for using VirSim. You enter them on the
vcs command line and also specify the source files.
Options for Using VirSim interactively with VCS
+++++++++++++++++++++++++++++++++++++++++++++++
-RI
Run Interactive. Starts VirSim immediately after compilation.
-RIG
Run Interactive Debug. Start VirSim using an existing executable
file (such as the simv or simv.exe file). VCS does no compilation.
+sim+<simv_name>
Use with the -RIG option. You need this option to specify the name
of the simv executable file that isn't named simv but has a different
name that you specified with the -o compile-time option.
+vslogfilesim[+<filename>]
Enables the logging of VCS communication messages in the VirSim log
file. If you use both +vslogfile and +vslogfilesim, VirSim commands
and VCS messages are saved to the same file.
If you do not specify a filename, the log is automatically saved
to the working directory as VirSim.log.
+vpdfile+<filename>
At runtime, defines an alternative name of the VCD+ file that VCS
writes instead of the default name vcdplus.vpd. Options for Using VirSim in Post-Processing
+++++++++++++++++++++++++++++++++++++++++++
-RPP
Run Post-Processing mode. Starts VirSim for post-processing a VCD+
file.
+vcdfile+<filename>
Specifies the VCD file you want to use for post-processing.
+vpdfile+<filename>[+start+<start_time>+end+<end_time>]
In post-processing, specifies the VCD+ file you wish to view in
VirSim. The optional +start+<start_time> and +end+<end_time>
arguments specify you only want VirSim to display the results
from between these simulation times. Options for Specifying How VCS Writes the VCD+ File
+++++++++++++++++++++++++++++++++++++++++++++++++++
-PP
Enables system tasks and options for VCD+ files and optimizations
for faster post-processing.
-I
Enables system tasks and options for VCD+ files.
+vpdbufsize+<MB>
VCS uses an internal buffer to store value changes before it writes
them to the VCD+ file on disk. VCS makes this buffer size either 5
MB or large enough to record 15 value changes for all nets and
registers in your design, which ever is larger.
You can use this option to override the buffer size that VCS
calculates for the buffer size. You specify a buffer size in
megabytes.
+vpddrivers
Tells VCS to record the values of all the drivers of all the nets.
+vpdfilesize+<MB>
Specifies the maximum size of the VCD+ file. When VCS reaches this
limit, VCS overwrites the oldest simulation history data in the file
with the newest.
+vpdignore
Tells VCS to ignore $vcdplus system tasks so VCS does not write a
VCD+ file.
+vpdports
Tells VCS to record, in the VCD+ file, the port direction of signals
that are ports.
+vpdnocompress
Disables the automatic compressing of the data in VCD+ files.
+vpdupdate
If VCS is writing a VCD+ file during simulation, this option enables
you to have VCS halt writing to the VCD+ file while the simulation
is running and so that you can view the recorded results in VirSim.
This option enables you to use the update feature in VirSim.
+vpdnostrengths
Disables recording strength information in the VCD+ file. Options For CAlling The vcd2vpd and vpd2vcd Utilities
*****************************************************
-vcd2vpd <vcd_filename> <vcdplus_filename>
Tells VCS to find and run the vcd2vpd utility that converts a VCD
file to a VCD+ file. VCS inputs to the utility the specified VCD
file and the utility outputs the specified VCD+ file.
-vpd2vcd <vcdplus_filename> <vcd_filename>
Tells VCS to find and run the vpd2vcd utility that converts a VCD+
file to a VCD file. VCS inputs to the utility the specified VCD+
file and the utility outputs the specified VCD file.
The Virsim debugger and the vpd2vcd and vcd2vpd translator utilities
are best invoked via the vcs command line. Summary of vcs options for the $vcdpluson tasks:
------------------------------------------------
-I enable interactive/postprocessing debugging capabilities
-PP enable optimizer postprocessing capabilities for vcd+
+vcsd enable the VCS DKI (Direct Kernel Interface); +vpdports,
+vpddrivers, output and interactive
simulation currently are not available in +vcsd mode. Summary of vcs options for the Virsim GUI:
------------------------------------------
-RI after compilation, run simulation under Virsim (implies -I)
-RIG run simulation under Virsim without compiling (executable has to exist)
-RPP run Virsim in postprocessing mode (requires file created by $vcdpluson) Additional Virsim Verilog and $vcdpluson flags:
-----------------------------------------------
VirSim 4.3.R11 Virtual Simulator Environment
Copyright (C) 1993-2003 by Synopsys, Inc.
Licensed Software. All Rights Reserved.
Usage: vcs [-RI|-RIG|-RPP] [[+vpdfile+<vpdname>]...] [[+vcdfile+<vcdname>]...] [[+cfgfile+<cfgname>]...]
[sim-opts] [vpd-opts-to-pli] [other-opts] files
+vpdfile+<vpdname> Multiple VPD files can be opened using several
+vpdfile+ commands
+vcdfile+<vcdname> Multiple VCD files can be opened using several
+vcdfile+ commands
+cfgfile+<cfgname> Multiple (incremental) configuration files can be loaded
sim-opts:
+sim+<simulator-path> Sets simulator path name
+simtype+<simulator> Sets simulator type exactly as listed in Simulator
Invocation Dialog
+simargs+<parameters> Sets additional simulator arguments. Double quotes
around multiple arguments.
+simargs+"+vpdfile+<vpdname>" Sets name of VPD file to be created by VCD+ PLI
vpd-opts-to-pli: Options for VCD+ generation by an interactive
simulation run started by virsim
+vpdports Stores port type information for hierarchy
+vpddrivers Stores data for changes on drivers of resolved nets
+vpdbufsize+<#MB> Changes the default size of the internal VCD+ buffer
+vpdfilesize+<#MB> Sets file size when storing data in wraparound mode
+vpdupdate Enables VPD file locking
+vpdignore Tells simulator to ignore all calls to generate VPD
+vslogfile Enables message logging. Does not log simulation communication messages
+vslogfile+<filename> Enables message logging. Logs messages in filename
+vslogfilesim Enables logging of simulation communication messages
other-opts: Sets regular options to compile verilog code
+v2k Enables supported verilog 2000 additions
files: Verilog source code file(s) list Summary of vcd2vpd options:
---------------------------
Usage: vcs -vcd2vpd <options> <evcd_options> <vcd_file> <vpd_file>
<options>
-b# Buffer size in KB used to store Value Change Data before
writing it to disk.
-f# Maximum output file size in KB. Wrap around occurs if
the specified file size is reached.
-h Translate hierarchy information only.
-m Give tranlsation metrics during translation.
-q Suppress printing of copyright and other informational messages.
+deltacycle Add delta cycle information to each signal value change.
+glitchon Add glitch event detection data.
+nocompress Turn data compression off.
+nocurrentvalue Do not include object's current value at the beginning of each VCB.
<evcd_options>
+dut+<dut_prefix> Modifies the string identifier for the Device-Under-Test
half of the split signal. Default is "DUT".
+tf+<tf_prefix> Modifies the string identifier for the Test-Fixture
half of the split signal. Default is "TF".
+indexlast Appends the bit index of a vector bit as the last
element of the name. Summary of vpd2vcd options:
---------------------------
Usage: vcs -vpd2vcd <vpd_file> [<vcd_file>]
Summary of vpd2vcd command line options
-h Translate hierarchy information only.
-q Suppress printing of copyright and other informational messages.
-s Allow sign extension for vectors. Reduces size of <vcd_file>.
-x Expand vector variables to full length when displaying
$dumpoff value blocks.
+zerodelayglitchfilter Zero delay glitch filtering for multiple value changes within
the same time unit.
+morevhdl Translates the vhdl types that are not directly mappable to
verilog types in addition to the ones that are mappable.
+start+<value> Translate value changes starting after start time <value>
+end+<value> Translate value changes ending before end time <value>
(Note) If both start and end values are input, value changes
occuring between start and end time are translated.
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